Every story tagged Semiconductor Technology, curated for CIOs and IT leaders — ranked by source credibility, engagement, and freshness.
5 stories · open in the command center
Pat Gelsinger, former Intel CEO, is leveraging deep tech venture capital to address the semiconductor industry's critical bottleneck: advancing lithography technology to extend Moore's Law and meet explosive AI-driven chip demand. As a general partner at Playground Capital with a board seat at portfolio company xLight, Gelsinger is betting that breakthroughs in nanometer-scale light-based chip manufacturing—potentially moving beyond the current 13.5-nanometer standard—are essential to unlocking the next generation of processor capabilities. This shift reflects a broader market acceleration where the semiconductor industry's trillion-dollar milestone is moving from 2030 to 2025, creating unprecedented investment opportunities for deep tech firms with credible founding teams and proven physics.
QuantumDiamonds has secured €91M in funding to commercialize quantum sensing technology for semiconductor defect detection, with significant backing from the European Chips Act, signaling strategic European investment in advanced manufacturing quality assurance. This breakthrough positions quantum-enabled inspection as a critical competitive advantage in chip production, requiring IT leaders to evaluate how quantum technologies may reshape semiconductor supply chain resilience and manufacturing intelligence. Organizations dependent on high-reliability semiconductors should anticipate how quantum defect detection will become table-stakes for supply chain qualification and quality assurance in coming years.
Samsung has successfully demonstrated 3D Stacked FETs with triple nanosheet channels at 42nm, achieving a breakthrough in transistor density by vertically stacking n-type and p-type transistors rather than placing them side-by-side, enabling significantly more processing power within the same chip footprint. This advancement represents the natural evolution of semiconductor architecture and addresses the physical limitations of traditional planar designs, directly impacting the performance and power efficiency capabilities of next-generation computing devices that IT organizations will deploy. For technology leaders, this signals that Samsung's roadmap will deliver higher computational density and efficiency gains in future processors, requiring IT infrastructure planning to account for improved performance characteristics and potentially shifted thermal and power management profiles.
Huawei is successfully rebuilding its domestic chip capabilities using innovative logic-stacking technology to circumvent U.S. export restrictions, potentially reshaping global semiconductor supply chains and reducing dependence on Western technology providers. This development has significant implications for IT organizations relying on diversified supply chains, as geopolitical chip restrictions may force reconsideration of vendor strategies and alternative sourcing for critical components. Technology leaders should anticipate increased competition in semiconductor markets and potential shifts toward region-specific technology ecosystems that could affect long-term infrastructure planning and vendor lock-in risks.
Researchers have demonstrated a scalable manufacturing process for monolithic 3D silicon chips that vertically stack circuits while respecting thermal constraints, potentially extending Moore's Law beyond the physical limits of traditional 2D transistor scaling. This breakthrough enables dramatic increases in computing density, speed, and energy efficiency—particularly valuable for AI and data-intensive workloads—while achieving production-ready device yields of 98-100%. IT leaders should anticipate a new generation of processors with fundamentally improved performance characteristics that could reshape infrastructure planning, reduce power consumption, and enable denser deployments of AI accelerators and high-performance computing systems.