Chips, Memory, and Power | Pat Gelsinger

Pat Gelsinger, now at Playground Global and formerly CEO of Intel and VMware, joins a16z’s Ragu Raguram and Guido Appenzeller to map the next bottlenecks in AI infrastructure. He argues AI is making chip design easier but pushing constraints into fab time, memory, power, networking, and data-center energy capacity—issues CIOs will need to plan around as AI clusters scale.

Key points

• AI will compress chip design cycles, but manufacturing still takes months, creating a big mismatch between design speed and time-to-use.
• Memory is the next major hardware frontier: HBM is still the best option, but new memory architectures and materials are finally becoming viable.
• Power is an upper bound on AI growth; Gelsinger expects more data-center project defaults if electricity supply lags GPU demand.
• Optical interconnects are likely to replace much copper, especially for scale-up AI clusters and future optical switching.
• He expects today’s flood of highly specialized AI chips to consolidate as workloads evolve, capital concentrates, and software stacks mature.
• VMware-like abstraction and management will need to be rebuilt for agent swarms, with policies, security, and performance controls for AI agents.